Design of power efficient modular FIR filters based on reduced multiconstant multipliers
Abstract
Design of power efficient modular FIR filters based on reduced multiconstant multipliers
Incoming article date: 29.11.2017Currently, issues of development of power efficient hardware blocks for digital signal processing (DSP) devices gain special importance. This is due to the rapid flourishing of wearable electronics, the Internet of things (IoT), network and telecommunication systems. The key component of many DSP devices is a finite impulse response (FIR) filter. It is not surprising that currently a large number of scientific papers are devoted to the development of power efficient FIR filters. The article proposes an original approach to the issue solution. As a methodological basis, modular arithmetic was chosen, already proven as an effective mathematical apparatus for the development of high-speed DSP devices. Another solution was the use of the FIR filter transposed form and methods for constructing the reduced blocks of the multiconstant multipliers. The experimental part demonstrated the efficiency of the block reduction methods of the multiconstant multiplication from the point of view of the filter power consumption. The article also made recommendations for the use of the proposed methods for specific implementations of the FIR filters.
Keywords: modulo FIR filter, multiconstant multiplier, transposed form, power consumption, dissipated power