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An improved method of FPGA implementation of systems of logical functions specified in PDNF

Abstract

An improved method of FPGA implementation of systems of logical functions specified in PDNF

Tyurin S.F., Vikhorev R.V.

Incoming article date: 14.03.2017

At present, field programmable gate arrays are in high demand at design of automation and control devices. The basis of field programmable gate array logic element is the generator of functions of N variables, which is often called Look-up Table (LUT). LUT is based on a multiplexer and constructed as a tree of elementary multiplexers 2:1. LUT tuning is realizing by loading the constants to the inputs of static random access memory. At the article the simplest LUT with one variable is analyzed in detail. But the existing logical element has a deficiency. It is that M LUTs are required to implement M logic functions. In the CMOS transistors used in the LUT, drain nodes and sources are equivalent which allows reversing the signals. Based on this, there is proposed the LUT decoder (DC-LUT). A detailed description of the DC-LUT is provided at the article. The implementation of DC-LUT with a large number of variables is also considered. The proposed structure of DC-LUT allows implementing a system of logical functions that depend on conjunctions of a perfect disjunctive normal form more effective, in contrast with the existing solution.

Keywords: field-programmable gate array, look-up table, the system of logical functions, perfect disjunctive normal form